1. Field of the Invention
The present invention relates to a digital-to-analog converter (DAC), and more particularly, to a DAC for a display device which generates a gradation voltage according to input data.
2. Description of the Related Art
A display device, such as a liquid crystal display (LCP), a plasma display panel (PDP), an organic light-emitting diode (OLED) display, etc., uses a DAC to decode digital data that are inputted from an external source so as to convert the data into an analog gradation voltage. The gradation voltage is then used to drive each pixel R,G,B and thereby display a desired image.
For example, each pixel R, G, B of an LCD exhibits nonlinear light transmission characteristics. To achieve linearity with respect to such nonlinear light transmission, gamma correction is performed in a DAC of a source driver which drives the pixels. Gamma correction is effective in obtaining a linear relation between a voltage applied to the pixels and light transmission.
To operate a liquid crystal panel of the LCD, a voltage is applied to liquid crystals such that light emitted from a backlight is adjusted and a desired image is displayed. Since the light transmission characteristics of each pixel are different, the LCD must adjust the light transmission of each pixel (R,G,B) differently in order to accurately display the desired image on the liquid crystal panel.
However, even with such differences in light transmission for each pixel R,G,B, existing approaches still are not able to perform control such that the light transmission of each pixel is precisely transmitted to each pixel due to the fact that with such existing approaches, the gradation scale value of each pixel is identically designed in the DAC on the basis of a specific pixel. As a result, the color tone appearing on the liquid crystal panel is unnatural. That is, the color tone of objects appearing on the liquid crystal panel is different from the actual color tone.
Hence, to overcome this drawback, there is a need for a linear DAC that allows a high resolution to be obtained by the display device to which the DAC is applied.
FIG. 1 is a schematic circuit block diagram of a conventional DAC 10. The DAC 10 of FIG. 1 includes a gradation voltage generator 11, a decoder 13, a switch controller 15, and a buffer 17.
The gradation voltage generator 11 includes a plurality of resistors connected in series to thereby generate dissimilar gradation voltages via the different voltage drops across the resistors. The decoder 13 receives signals of upper n bits in a parallel input signal of k bits, and selects switches corresponding to the input n bits so as to output a gradation voltage corresponding to the gradation voltage generator 11 through a first reference line (VREFL). During this operation, the decoder 13 also selects a gradation voltage adjacent to the selected gradation voltage and outputs the same through a second reference line (VREFH).
The switch controller 15 receives signals a of lower m bits in the parallel input signal of k bits, and according to input data of the m bits, controls a plurality of internal switches (not shown) such that the first and second reference lines (VREFL, VREFH) are connected to a plurality (2m) of output lines, and the signals inputted through the first and second reference lines (VREFL, VREFH) are multiplexed and outputted through each of the 2m output lines. The buffer 17 receives the signals outputted by the switch controller 15 and performs interpolation to effect buffering, after which a resulting gradation voltage VOUT is outputted through an output terminal of the buffer 17.
In the conventional DAC 10 configured and operating as in the above, in order to realize a high grayscale, the gradation voltage generator 11 must utilize 2n resistors, where n is the number of bits of digital data inputted to the decoder 13, and the switches of the decoder 13 are needed to select the generated gradation voltages. Accordingly, if it is desired to achieve an improvement in resolution of n bits, the circuit area is increased exponentially (2n), and at the same time, an operating reference voltage for expressing grayscale must be extremely large and precise.
To overcome these problems, a conventional DAC has been proposed that utilizes two decoders, each associated with an array of resistors. An example of such conventional DAC is shown in FIG. 2.
FIG. 2 is a schematic circuit block diagram of another conventional DAC 50. The DAC 50 of FIG. 2 includes a first gradation voltage generator 51, a first decoder 52, a pair of buffers 53, 54, a second gradation voltage generator 55, a second decoder 56, a switch controller 57, and another buffer 58.
The first gradation voltage generator 51 includes a plurality of resistors connected in series to generate dissimilar gradation voltages via the different voltage drops across the resistors. The first decoder 52 receives upper n bits in a parallel input signal of k bits, and selects switches corresponding to the input n bits to output a corresponding gradation voltage of the first gradation voltage generator 51 through a first reference line V′REFL. During this operation, the first decoder 52 also selects a gradation voltage adjacent to the selected gradation voltage and outputs the same through a second reference line V′REFH.
The buffers 53, 54 perform buffering of the signals outputted through the first and second reference lines V′REFL, V′REFH to stabilize the signals, after which the stabilized signals are outputted to the second gradation voltage generator 55.
The second decoder 56 receives lower m bits in the parallel input signal of k bits, selects switches corresponding to the input m bits, and outputs a corresponding gradation voltage of the second gradation voltage generator 55 through each of third and fourth reference lines V″REFL, V″REFH.
The switch controller 57 receives signals of lowermost j bits in the parallel input signal of k bits, and according to the input j bit data, controls a plurality of internal switches (not shown) such that the third and fourth reference lines V″REFL, V″REFH are connected to a plurality (2j) of output lines, and the signals inputted through the third and fourth reference lines V″REFL, V″REFH are multiplexed and outputted through the 2j output lines. The buffer 58 receives the signals outputted by the switch controller 15 and performs interpolation to effect buffering, after which a predetermined gradation voltage VOUT is outputted through an output terminal of the buffer 58.
In FIG. 2, each of the first and second decoders 52, 56 is associated with an array of resistors for dividing the voltage applied thereto, and includes switches for outputting analog voltages corresponding to the digital data in the voltages outputted by the set of resistors.
Further, the first decoder 52 and the second decoder 56 are interconnected via the buffers 53, 54. This ensures that the voltage levels divided by the first decoder 52 are not influenced by the array of resistors of the second gradation voltage generator 55.
That is, in FIG. 2, the analog values outputted through the n-bit and m-bit first and second decoders 52, 56 are inputted to the switch controller 57, and following the interpolation operation of the j-bit buffer 58, the final analog gradation voltage VOUT is outputted through the output terminal of the buffer 58.
This conventional DAC 50 also suffers from an increase in circuit area due to the fact that two buffers 53, 54 are used therein.
Moreover, due to an offset voltage of the buffers 53, 54, the degree of precision of this conventional DAC 50 is limited by at least an amount corresponding to the offset voltage of the buffers 53, 54.
Additionally, the greater the number of bits of the data that needs to be processed, the greater the number of the resistors of the gradation voltage generators 51, 55 and the number of the decoders 52, 56. This results in an exponential increase in the size of the DAC 50. Typically, an increase in the number of bits by n results in a 2n increase in the size of the DACs 10, 50 of FIGS. 1 and 2.
Since the decoders 52, 56 of FIG. 2 divide the signal of k bits to process either n bits or m bits, they are smaller in size than the decoder 13 of FIG. 1. However, due to the use of the additional resistors for voltage division and an additional buffer for error reduction in the output voltage in the DAC 50 of FIG. 2, the DAC 50 of FIG. 2 remains large.